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Zhengdong Huang (黄政东)

Third-year Undergraduate Student @ Southern University of Science and Technology (SUSTech)

Projects

🚦 YOLC | Traffic Sign Detection and Recognition Research

Project Score: 96 out of 100
Role: Main Contributor 👑
Date: Dec. 2024 📅

  • 🔍 Systematically investigated the field of Traffic Sign Detection and Recognition, conducting a detailed analysis of domain challenges and data characteristics.
  • 💡 Proposed a novel model and training framework (YOLC) to tackle long-tail data distribution and improve detection accuracy, significantly enhancing detection and classification performance on open-source datasets.
  • 📚 Course Project: Machine Learning (H) , collaborated with another student from the Turing Class. 🤝

📚 CourseDemo | Online learning platform based on Distributed Architecture

Project Score: 97 / 100
Role: Main Contributor 👑
Date: Oct.-Nov. 2024 📅

  • 🗂️ GitHub: FrostyHec/CourseDemo
  • 📝 An Online Video Learning Platform based on Distributed Architecture
  • 🛠️ Tech Stack: SpringBoot, Vue3, Flask, Docker, Nginx, Kubernetes, PostgreSQL, MinIO
  • 📚 Course Project: Cloud Computing with Big Data (NUS Summer Workshop), collaborated with 3 classmates 🤝

👥 Group Up | Web Application in Microservice Architecture

Project Grade: A
Role: Main Contributor 👑
Date: Jun.-Jul. 2024 📅

  • 🗂️ GitHub: FrostyHec/GroupUp_NUS_SWs_Project
  • 📝👥 Web application that helps organizers group people based on questionnaire analysis.
  • 🛠️ Tech Stack: Spring Cloud, Next.js, Flask, Vectorization & LLM 🤖, Kubernetes, PostgreSQL, Redis, RabbitMQ, AWS ☁️
  • 📚 Course Project: Cloud Computing with Big Data (NUS Summer Workshop), collaborated with 3 classmates 🤝

⚙️ CPUdemo | Multi-cycle RV32I CPU Design

Project Score: 115 + / 100 🏅
Role: Main Contributor 👑
Date: Mar.-May 2024 📅

  • 🗂️ GitHub: FrostyHec/CPUdemo
  • 🚀 Lightweight CPU core on Minisys featuring parallel processing, branch prediction, and interrupt/exception handling; supports RV32I & Zicsr instructions and multiple graph/IO devices.
  • 💻 Implemented with Chisel, Verilog, C, and RISC-V Assembly.
  • 📚 Course Project: Computer Organization (H), teamed with 2 fellow Turing Class students 🤝

🌐 RDT-Socket

Project Score: 118 / 100 🏅
Role: Main Contributor 👑
Date: May 2024 📅

  • 🗂️ GitHub: RDT-Socket
  • 🖥️✨ A Reliable Data Transfer(RDT) protocol implemented based on UDP, supporting mechanisms such as stable connection establishment, packet loss and corruption detection, retransmission waiting, parallel transmission, and optimization for large data volume transfer.
  • 📚 Course Project: Computer Network — Project 2, teamed with 2 fellow students 🤝

🌐 DNS Server

Project Score: 100 / 100 🏅
Role: Individual Contributor 👑
Date: Mar. 2024 📅

  • 🗂️ GitHub: Developing DNS Servers
  • 🖥️✨ Built a lightweight DNS server that accurately handles DNS packet reception 📦, parsing 🔍, and recursive querying 🔄, delivering reliable name-resolution services for networks 🌐.
  • 📚 Course Project: Computer Network — Project 1

🗄️ ORMini | Lite Object-Relational Mapping Framework for Java

Type: Personal Open-source Project 🌱
Role: Individual Contributor 👑
Date: Nov. 2023 📅

  • 🗂️ GitHub: FrostyHec/ORMini
  • ⚡ Lightweight ORM framework inspired by MyBatis; supports XML/YAML configuration, object mapping, batch & transaction execution.
  • 🔧 Utilizes extensive design patterns to enhance scalability and performance 🚀

♞ DarkChess | Desktop Chinese Dark Chess Game

Project Score: 120 + / 100 🏅
Role: Main Contributor 👑
Date: Nov. – Dec. 2022 📅

  • 🗂️ GitHub: FrostyHec/DarkChess_CS107FinalProject
  • 🎮 Chinese Dark Chess game supporting man-machine and online multiplayer modes; includes animations, SFX 🔊, leaderboards 🏆, and custom settings ⚙️
  • 💻 Implemented with JavaFX; ready-to-use releases for Windows 🪟
  • 📚 Course Project: Introduction to Computer Programming (H), co-developed with a Turing Class teammate 🤝